A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.
More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design
Enabling greater reliability, scalability and flexibility of GPU emulation at AMD using a hybrid virtual-machine based approach
How AMD coupled a virtual PC and transaction-based emulation to accelerate the verification of its latest GPU
This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
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