Verification

January 20, 2016
End to end prototyping - featimg

Using end-to-end prototyping to reduce the impact of rising software content in SoCs

A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
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January 19, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Reachable or reached, covered or coverable – is it just semantics?

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
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January 18, 2016
How to debug and verify finite state machines early in the design flow

Finite state machines: How to debug and verify them early in the flow

Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
January 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Thought you had verified your SoC? You probably only did half…

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
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January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
December 16, 2015
How to expose X-optimism issues in ASIC and FPGA Design by Lisa Piper

Fix X-pessimism in netlists with practical techniques

Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.
December 9, 2015
Emulation IoT Networking Challenges

Emulation overcomes the five main IoT and networking verification challenges

More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
November 30, 2015
TDF_DS featimg

How to accelerate FPGA design productivity at every available step

How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design
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November 23, 2015
AMD VirtualBox hybrid emulation - featdiag

Enabling greater reliability, scalability and flexibility of GPU emulation at AMD using a hybrid virtual-machine based approach

How AMD coupled a virtual PC and transaction-based emulation to accelerate the verification of its latest GPU
November 2, 2015
Verification IP for greater productivity

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
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