A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.
How the powertrain of an electric vehicle is modeled first in software, then elaborated using virtual hardware running target code, to enable virtual FMEA with rich data-gathering and analysis capabilities.
Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
How fault mode and effect analysis (FMEA) can be performed on a virtual prototype of an automotive system containing mechanical, electrical, analog and digital models, including the microcontroller running the same software as will be used in the car.
The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
What can you add to a challenging project without pushing out deadlines and muddling communication?
Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
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