How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.
Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
How staging virtual prototype bring-up can accelerate the development of embedded software in complex systems.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
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