How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Achieving ISO 26262 certification for advanced driver assistance systems takes a combination of ASIL ready IP and rigorous development strategies.
Introducing one of the latest refinements of formal and showing how ArterisIP and Oski Technology used the strategy on an ARM-based design.
Ashish Darbari concludes his series on the need for new verification strategies by considering Debug and Signoff & Review.
Richard Pugh shows how the fast-growing market for drone silicon highlights emulation's power where high data volumes are critical.
In part two of this series, Ashish Darbari introduces a checklist to address verification challenges and build the meta model.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
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