Verification

December 4, 2017
Richard Pugh featured image SSD expert insight

Data-hungry applications demand emulation

Richard Pugh shows how the fast-growing market for drone silicon highlights emulation's power where high data volumes are critical.
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November 29, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The crisis of confidence facing verification II

In part two of this series, Ashish Darbari introduces a checklist to address verification challenges and build the meta model.
November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
November 6, 2017

Using sequential equivalence to verify clock-gating strategies

Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
October 31, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The crisis of confidence facing verification

Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
October 30, 2017
Debug case study for ARM/AXI based design

Case study: Verifying and optimizing software for power on SoCs

How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
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September 14, 2017
Featured image - Silicon photonics

Silicon photonics moves out of the shadows

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
August 31, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The evolution of formal verification – Part Two

Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
August 30, 2017
DTCO for early lithography issue identification - featured image

Your next node: find lithography issues early with DTCO

Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
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