Verification

February 4, 2014
Featured image - virtual prototyping big.Little case study

Debugging with virtual prototypes – Part Four

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
January 27, 2014
Atrenta CDC

Spot the difference between false and real clock violations

Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
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January 21, 2014
Cadence Palladium cluster

Productivity, predictability and versatility drive verification environments

Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.
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January 15, 2014
Featured image for Debugging with VPs - III

Debugging with virtual prototypes – Part Three

This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.
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January 13, 2014
Formal verification aids RTL verification

Formal verification enables Agile RTL development

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.
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December 23, 2013
Featured image Marvell case study

Better management of timing closure and optimization

How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
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December 16, 2013
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Consistency key to gaining the advantages of IP integration

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
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December 8, 2013

Debugging with virtual prototypes – Part Two

The second part of our series illustrates VP tools and techniques using the familiar example of Linux bring-up on an ARM-based SoC.
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November 14, 2013
Cadence virtual prototyping

A map of the prototyping ecosystem

Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
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November 11, 2013
Brian Fuller is editor in chief at Cadence Design Systems.

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
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