May 15, 2014
While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
April 22, 2014
Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
April 16, 2014
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
April 16, 2014
Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
March 24, 2014
An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.
March 17, 2014
Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
February 27, 2014
The next boost to verification productivity will come from the integration of multiple strategies and tools.
February 26, 2014
Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification
February 26, 2014
Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
February 6, 2014
The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.