Verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.