Verification

Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations

Compliance with aviation’s hardware design standard is seen as a ‘tough ask’, but EDA’s own evolution has made that process easier than you may think.

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.