Back to basics – doing formal the right way
Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Verification
Verifying MIPI interfaces in SoCs
Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
Technology trends demand netlist-level CDC verification
Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
Smaller designs face greater risk of respins
Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
Verifying clock domain crossings when using fast-to-slow clocks
A look at three techniques to verify the validity of signals moving between clock domains
Fixing late ECOs in ARM core subsystems at STMicroelectronics
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
Achieving safety and security in SoC development
Designers will have to update development processes to achieve the rigorous safety certifications required in automotive, rail, avionics and similar markets
Putting emulation on the map
Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Enabling FPGA prototyping of large ASIC and SoC designs
How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
Developing and integrating configurable GPU IP using FPGA-based prototyping
How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
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