In part two of this series, Ashish Darbari introduces a checklist to address verification challenges and build the meta model.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.
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