Verification

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering

What can you add to a challenging project without pushing out deadlines and muddling communication?

Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.

How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.

A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.

Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.

Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.