Verification

Considering the issue of functional safety verification in automotive systems design, within the context of ISO26262

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.

Engineers developing an SoC for the automotive market have to show that it doesn’t have functional safety issues - even if the SoC enters an unexpected state. Here's how to tackle the safety verification task.

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.

Emulators have come a long way since their first introduction nearly three decades ago.

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.