November 6, 2017
Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
October 31, 2017
Why is verification still such a challenge in spite of all the technologies and techniques being brought to bear
October 30, 2017
How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.
October 27, 2017
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
September 14, 2017
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
August 31, 2017
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
August 30, 2017
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
July 25, 2017
This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.
July 21, 2017
Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
June 18, 2017
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
