EDA Topics

February 8, 2019
Featured image - Layout merging feature

Fast, accurate layout merging for SoC flows

How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
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February 6, 2019

Low-power debugging made easy

UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
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January 28, 2019

Emulation for AI: Part Two

The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
January 25, 2019

Emulation for AI: Part One

An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
January 25, 2019

A better way to manage error reporting at the chip and block levels

In a continuous-build design flow, at which level should your error markers be addressed?
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January 16, 2019
Virtual sequences with portable stimulus - featured image.

Create more flexible virtual sequences with Portable Stimulus

Virtual sequences are considered challenging to write and re-use. Learn how to overcome those issues with the new Portable Stimulus Standard in this DMA-based case study.
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January 7, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Introducing the ADEPT FV flow

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
December 31, 2018
MBH featured image

Enhanced model-based hinting may be the edge you need below 20nm

A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
December 11, 2018

Win on the fault campaign trail with formal

How formal verification for the ISO26262 automotive functional safety delivers the full activation, propagation, and observation in the form of proven and exhaustive results.
December 3, 2018
Rahul Chirania is a staff applications engineer with the static verification team at Synopsys.

Verifying clock domain crossings in UPF-based low-power SoCs

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
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