EDA Topics

December 3, 2018
Rahul Chirania is a staff applications engineer with the static verification team at Synopsys.

Verifying clock domain crossings in UPF-based low-power SoCs

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
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November 20, 2018
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Adding system-level, post-layout electrical analysis to HDAP design and verification

Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
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October 26, 2018
Philip Vanness is a product marketing manager at Mentor, a Siemens business.

8.8 billion miles to verify

How the digital twin can fuel automotive verification flows impossible in the real world.
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October 16, 2018
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Reliability verification: It’s all about the baseline

How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
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October 5, 2018
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How to improve throughput for gate-level simulation

Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
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October 3, 2018
Allen Watson of Synopsys

An open-source framework for greater flexibility in machine-learning development

Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
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September 20, 2018
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How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
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September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
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August 14, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
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