Expert Insights

Ashish Darbari  |  July 4, 2019

A new formal proof kit for RISC-V processors

Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
Paul Dempsey  |  June 18, 2019

The vocal persuader

In conversation with author and SEMICON West/ES Design West keynoter Bob Pearson on the challenges facing tech on external and internal communication.
Tom Anderson  |  June 18, 2019

A helping hand for design and verification

Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Dennis Joseph  |  June 11, 2019

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:   |  
Tom Anderson  |  May 15, 2019

Why hyperlinks are essential for HDL debugging

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
Topics: EDA - IC Implementation, Verification  |  Tags: , , , ,   |  Organizations:   |  
Lauro Rizzatti and Gabriele Pulini  |  May 14, 2019

How emulation’s virtual mode boosts productivity: Part Two

Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
Topics: EDA - DFT, Verification  |  Tags: , , ,   |  Organizations:   |  
Lauro Rizzatti and Gabriele Pulini  |  May 1, 2019

How emulation’s virtual mode boosts productivity: Part One

This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
Topics: EDA - DFT, Verification  |  Tags: , , ,   |  Organizations: ,   |  
Paul Dempsey  |  April 2, 2019

High-level synthesis for AI: Part Two

How Chips&Media used HLS on the development of a computer vision IP block.
Paul Dempsey  |  March 26, 2019

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
Bob Smith  |  March 15, 2019

Enabling the move to a system-centric view

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

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