Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
The argument for an integrated approach to SoC verification
How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
The encryption chain for today's highly collaborative designs needs to be managed with care.
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