Expert Insights

Anders Nordstrom  |  March 1, 2016

Exploiting the power of reset in formal verification

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
David Wiens  |  February 11, 2016

Where tools end and best practices begin

Learn how you can benchmark your design practices against the most successful players in the PCB market - and why you should.
Geoffrey Ying  |  February 10, 2016

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Lauro Rizzatti  |  January 27, 2016

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
Luke Collins  |  January 19, 2016

Reachable or reached, covered or coverable – is it just semantics?

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
Topics: EDA - Verification  |  Tags: , ,   |  Organizations:   |  
Angela Raucher  |  January 12, 2016

Processor configuration for low-power IoT applications

Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Topics: IP - Assembly & Integration, Selection  |  Tags: , ,   |  Organizations:   |  
Walden Rhines  |  January 11, 2016

2016 – A continuation of change

Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
Anders Nordstrom  |  January 5, 2016

Thought you had verified your SoC? You probably only did half…

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Walden Rhines  |  January 4, 2016

2015 – The year in review

Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.
Topics: EDA Topics  |  Tags: , , , , , ,   |  Organizations:   |  
Steve Pateras  |  December 29, 2015

Memory BIST for automotive designs

Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
Topics: EDA - DFT  |  Tags: , , , , ,   |  Organizations:   |  

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