Expert Insights

Neel Desai  |  May 30, 2013

Enabling greater productivity and schedule predictability in IC design

How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
Graham Bell  |  May 14, 2013

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Mick Posner, Synopsys  |  April 24, 2013

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Michael Sanie, Synopsys  |  April 4, 2013

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Steve Pateras  |  November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,   |  

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