Expert Insights

Nasib Naser  |  October 19, 2015

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Amol Herlekar  |  October 8, 2015

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Topics: IP - Design Management, EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Gervais Fong  |  August 26, 2015

USB Type-C: easier for users, harder for designers

Implementing the reversible connector of USB Type-C demands a rethink of the PHY architecture to achieve the most cost-effective IP solution
Topics: IP - Selection  |  Tags: , , , ,   |  Organizations:   |  
Warren Kurisu  |  August 24, 2015

A scalable RTOS and other essentials for embedded wearables development

The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
Jai Durgam  |  August 19, 2015

Make vs buy in automotive IP

A look at some of the quality and safety requirements that must be met when developing and applying semiconductor IP to the automotive sector.
Topics: IP Topics, IP - Selection, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:   |  
Luke Collins  |  June 25, 2015

Applying agile techniques to IC design

How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
Michael Thompson  |  April 20, 2015

Neural networks bring advanced object detection to embedded vision

Dedicated processors using convolutional neural networking techniques bring advanced vision techniques such as object recognition to embedded systems.
Ron Lowman  |  January 7, 2015

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
Yervant Zorian  |  October 10, 2014

Finding and fixing faults in finFET memories

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , , , ,   |  Organizations:   |  
Prasad Saggurti  |  August 27, 2014

Six key criteria for deciding to migrate to a finFET process

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Topics: EDA - IC Implementation, IP - Selection  |  Tags: , ,   |  Organizations: , , , , ,   |  

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