Expert Insights

Michael Thompson  |  May 24, 2017

Building processors to enable intuitive human-machine interaction

The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
Topics: IP - Selection  |  Tags: , , ,   |  Organizations:   |  
Ashish Darbari  |  May 22, 2017

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
Paul Dempsey  |  May 15, 2017

The Wally Rhines interview – Part Two: AI, automotive and security

This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
John Swanson  |  May 9, 2017

Building faster data centers with 25G Ethernet

The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , ,   |  Organizations: ,   |  
Paul Dempsey  |  May 8, 2017

The Wally Rhines interview – Part One: Mentor as a Siemens business

Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
Sanjana Bhattacharya  |  April 26, 2017

Eight tips for performing effective unreachability analysis

Unreachability analysis can help find design code that can never be executed, helping verification engineers refine their coverage goals.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Ron Press  |  April 10, 2017

Drawing on hierarchical DFT to benefit all designs and flows

Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
Topics: EDA - DFT  |  Tags: , , ,   |  Organizations: ,   |  
Anders Nordstrom  |  March 28, 2017

Are you testing your test?

Using formal core coverage to understand the effectiveness of formal coverage verification strategies in SoC design.
Paul Dempsey  |  March 15, 2017

DVCon China launches this April in Shanghai

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Anders Nordstrom  |  March 9, 2017

The art of abstraction

Successful FPV of large designs requires that parts of the design are abstracted. Learning how and where to apply abstractions will result in more proven properties and more bugs found.

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