The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
Unreachability analysis can help find design code that can never be executed, helping verification engineers refine their coverage goals.
Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
Using formal core coverage to understand the effectiveness of formal coverage verification strategies in SoC design.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Successful FPV of large designs requires that parts of the design are abstracted. Learning how and where to apply abstractions will result in more proven properties and more bugs found.
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