Expert Insights

Marco Casale-Rossi  |  November 16, 2012

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Anil Khanna  |  November 13, 2012

Embedded systems are evolving, but where are the tools?


Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
Topics: Embedded - Architecture & Design, Integration & Debug  |  Tags: ,   |  Organizations:   |  
Tong Gao  |  October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:   |  
Bill Neifert  |  September 18, 2012

Virtual prototyping moves further into the mainstream

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.
Topics: EDA - ESL, Verification  |  Tags:   |  
Antun Domic  |  September 6, 2012

Getting ready for 20nm

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Topics: EDA - DFM  |  Tags: , ,   |  Organizations:   |  
Pranav Ashar  |  August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Jürgen Schloeffel  |  July 3, 2012

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
Topics: EDA - DFT  |  Tags: , , ,   |  Organizations:   |  
Michael Buehler-Garcia  |  June 1, 2012

DAC 2012: 20(nm) questions

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Topics: EDA - DFM  |  Tags: , , , , ,   |  Organizations:   |  
Jeff Wilson, Mentor Graphics  |  May 22, 2012

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Topics: EDA - DFM  |  Tags: ,   |  Organizations:   |  
Richard Pugh, Mentor Graphics  |  April 25, 2012

No more spaghetti

Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  

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