Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
If you're going to be working on any aspect of multicore embedded system design, a newly published book titled "Real World Multicore Embedded Systems" will be an excellent guide.
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
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