Expert Insights

Piyush Sancheti  |  October 16, 2013

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:   |  
Axel Scherer  |  October 11, 2013

Learn the tricks of the UVM Register Layer

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
Adnan Hamid  |  October 7, 2013

Think like designers to fill the SoC verification gap

Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:   |  
Richard Goering  |  September 6, 2013

Real-world multicore embedded systems: review

If you're going to be working on any aspect of multicore embedded system design, a newly published book titled "Real World Multicore Embedded Systems" will be an excellent guide.
Tim Whitfield  |  August 25, 2013

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
Steve Smith  |  August 12, 2013

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,   |  
Dan Benua  |  July 25, 2013

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Graham Bell  |  July 3, 2013

The challenge of clock domain crossings – and some solutions

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Neel Desai  |  May 30, 2013

Enabling greater productivity and schedule predictability in IC design

How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
Graham Bell  |  May 14, 2013

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

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