Expert Insights - EDA

Steve Smith  |  August 12, 2013

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,   |  
Dan Benua  |  July 25, 2013

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Graham Bell  |  July 3, 2013

The challenge of clock domain crossings – and some solutions

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Graham Bell  |  May 14, 2013

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Graham Bell  |  May 7, 2013

Better analysis helps improve design quality

Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Mick Posner, Synopsys  |  April 24, 2013

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Marco Casale-Rossi  |  April 10, 2013

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
Topics: EDA - DFM, IC Implementation  |  Tags: , , ,   |  Organizations:   |  
Richard Goering  |  April 10, 2013

Focus on product creation for effective design

An increasingly important concept in design is that of product creation. An approach based on product creation looks beyond chip or board design.
Michael Sanie, Synopsys  |  April 4, 2013

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Neill Mullinger  |  January 24, 2013

Verification IP: the questions you should ask

How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  

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