Expert Insights - EDA

Michael Sanie, Synopsys  |  April 4, 2013

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Neill Mullinger  |  January 24, 2013

Verification IP: the questions you should ask

How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
David Fried  |  December 4, 2012

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Steve Pateras  |  November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,   |  
Marco Casale-Rossi  |  November 16, 2012

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Tong Gao  |  October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
Topics: EDA - DFM  |  Tags: , , , ,   |  Organizations:   |  
Bill Neifert  |  September 18, 2012

Virtual prototyping moves further into the mainstream

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.
Topics: EDA - ESL, Verification  |  Tags:   |  
Antun Domic  |  September 6, 2012

Getting ready for 20nm

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Topics: EDA - DFM  |  Tags: , ,   |  Organizations:   |  
Pranav Ashar  |  August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
J├╝rgen Schloeffel  |  July 3, 2012

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
Topics: EDA - DFT  |  Tags: , , ,   |  Organizations:   |  

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