Expert Insights - EDA

Graham Bell  |  May 14, 2013

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Graham Bell  |  May 7, 2013

Better analysis helps improve design quality

Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:   |  
Mick Posner, Synopsys  |  April 24, 2013

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,   |  
Marco Casale-Rossi  |  April 10, 2013

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
Topics: EDA - DFM, IC Implementation  |  Tags: , , ,   |  Organizations:   |  
Richard Goering  |  April 10, 2013

Focus on product creation for effective design

An increasingly important concept in design is that of product creation. An approach based on product creation looks beyond chip or board design.
Michael Sanie, Synopsys  |  April 4, 2013

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Neill Mullinger  |  January 24, 2013

Verification IP: the questions you should ask

How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.
Topics: EDA - Verification  |  Tags: ,   |  Organizations:   |  
David Fried  |  December 4, 2012

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Steve Pateras  |  November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Topics: IP - Assembly & Integration, EDA - DFT  |  Tags: , ,   |  Organizations: ,   |  
Marco Casale-Rossi  |  November 16, 2012

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.

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