What’s cooking at the Flash Diner?

By Zeeshan Yousuf |  No Comments  |  Posted: March 3, 2016
Topics/Categories: Embedded - Architecture & Design, IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , , ,  | Organizations:

Flash is the ice cream of memory technologies – everybody loves it. But you need to build the right verification environment to extract the greatest benefit.

Flash memory is an integral part of the devices around us. Already dominant in the mobile and photography markets, it is set to eclipse the use of hard-disk drives (HDDs) in more conventional computing devices, such as laptops and PCs.

The non-mechanical and non-volatile essence of flash memory makes it the perfect choice for compact mobile memory, such as micro Secure Digital (SD) memory cards. A flash memory drive has a material-based assembly that consists of electrons trapped between two gates — a control gate and a floating gate. If electrons are present between the gates, that represents a digital signal 1; if no electron is present, the digital signal is 0.

By contrast, an HDD is a metallic platter with a magnetic coating and read-write head that moves on a metallic platter. The read-write head is static when there is no power supply. One limitation of an HDD is that in the case of a shock, the head moves suddenly and the HDD is damaged.

Flash drives offer several other inherent benefits over HDDs.

  • Speed: To perform other tasks, a processor needs cycles free from memory read-write operations. Flash memory is blazingly fast and this provides shorter read-write cycles giving that extra time to the processor.
  • Durability: Because flash memory is material based, the data remains safe in an event of a shock or dropped device.
  • Quiet: Everyone likes devices that perform activities in near silence. Those that have flash memory make virtually no noise.
  • Form-factor variety: Flash memory cards come in various sizes. Thus, designers working on devices of different sizes and shapes have no issue finding form factors that match their configurations.
  • Lightweight: Flash memory is very compact in size. As a result, devices that use flash memory are lighter.

But flash memory does not only claim these advantages. It also speeds up the design development cycle. To get the full benefit of that, though, you need to be able to choose from the right menu of verification items.

Building a perfect verification environment in the shortest time is critical. Your environment should comprise comprehensive coverage plans and include assertions that ensure all specification violations are logged. Most importantly, it must have the flexibility to handle the plethora of host controller memory models supplied by different vendors.

Let’s first peruse the selection of compact memory cards on our Flash Diner’s menu. Then we will take an overview of what you must account for when selecting a verification environment and show you how to make your verification experience as easy, comprehensive, and fast as possible.

Secure Digital (SD)

SD is a non-volatile memory card format introduced in August 1999. It has become the industry standard. Just as diners and ice cream parlors entice us with many flavors and sizes of ice cream, SD cards offer a variety of options.

Figure 1. Flavors and sizes

Figure 1. Flavors and sizes

Figure 2. Flavors and sizes... again (Mentor Graphics)

Figure 2. Flavors and sizes... again (Mentor Graphics)

The card slot in a device varies according to the size of the SD card, not the type. The SDSC, SDHC, and SDXC types are used only for memory storage. However, an SDIO card can have input/output functionality (e.g., Bluetooth, Wi-Fi, RF, GPS). An SDIO card can be plugged into any SD card slot to behave like a storage card, but appropriate software support and a host controller must be installed in the device receiving it to use the input/output functionality. An SD card slot that supports SDIO supports all other SD cards.

Embedded Multimedia Card

An SD card serves as fast, mobile, compact, and non-volatile external memory. The Embedded Multimedia Card (eMMC) format is similar, but it is used for internal memory storage on PCBs. It is the first choice for such memory in most portable electronic products, including smartphones, tablets, and digital cameras.

To further understand eMMC, let’s visit the Flash Diner. The customers take a table, and order their food; the waiters serve the food. In this process, the customers do not need nor want to bother about how the food is prepared. They place an order and the chef takes care of preparation.

Figure 3. The Flash Diner serves eMMC (Mentor Graphics)

Figure 3. The Flash Diner serves eMMC (Mentor Graphics)

In this context, eMMC comprises an IC fixed to a circuit board. It contains the flash memory and flash memory controller on the same silicon die. The controller performs the same function as the chef. It takes the abstract instruction and performs the read-write operations in the flash memory, not showing how this is done. So, if eMMC is used in a circuit design for storage, it handles all the flash memory operations.

Open NAND Flash Interface

The chef and the pantry crew at the Flash Diner work in a well-organized manner and they have defined recipes for the dishes they offer. This enables the chef and his team to prepare the dishes efficiently and to consistently high quality.

Similarly, the Open NAND Flash Interface (ONFI) standardizes the low-level interface for NAND flash chips, reducing design time and also ensuring consistency. NAND flash is a commodity product used in consumer electronics, such as USB flash drives.

ONFI strengthens the compatibility and interoperability of NAND devices from different vendors. This increases the supply base for standard devices, cuts design time further and thereby accelerates time-to-market. The pin outs, packaging, and commands are almost the same for all NAND flash vendors. However, switching from one vendor to another can entail subtle differences in timing and command sets, which in turn can promote long debug cycles.

A VIP library for every taste

The Mentor Graphics Questa Verification IP (QVIP) library comprises a menu of state-of-the art predefined verification environments. These include UVM-based testbenches that allow users to seamlessly integrate QVIPs with their designs. All QVIPs provide comprehensive coverage plans and include assertions to ensure all specification violations are logged.

A basic concern in any memory design is the verification of its read/write feature. There are number of important concerns here. They include address ranges, single block and multiple block read/writes, multi-plane and cache read/writes, speed variation, and authorization. QVIP provides all the read/write checks to ensure the integrity of the read/write data on the memory.

Data integrity and parity checking is a must for all design verification. Design deals with data, and data is protected by a cyclic redundancy check (CRC), error-detecting code commonly used in storage to detect accidental changes to raw data. There are two aspects of the CRC mechanism: First, is the design generating the right CRC code? Second, in the case of a CRC error, what is the behavior of the design (i.e., is it according to the protocol)? QVIP has checkers and error injection mechanisms to cover all aspects of data integrity.

Timing parameters in different modes play an important role in memory design. It is requisite for every design that they are validated. Memory designs have host controllers and memory cards. The host and card can be from different vendors. Memory protocols provide standard time delays for data responses. Now, if the host or card do not follow the standard and they differ in timing for data responses, then they will not be compatible with each other. QVIP has checks for all timers to ensure the design is working correctly and no timer violation is happening.

All memory supports different classes of commands in different states. QVIP verifies all classes of command and their responses.

Error scenarios are fundamental to the design verification effort. Error scenarios help users verify design behavior and its recovery procedure. Such errors can involve invalid CRC, authentication, timing, invalid responses, and invalid commands – and more. QVIP provides error injection mechanisms appropriate to all types of error for memory design.

Mentor’s family of Flash QVIP is a one-stop solution for design houses looking for a verification solution for their memory designs. Because it supports all available memory models, a single QVIP testbench can cater to all the flash memory models with minimal changes.

The SD QVIP targets all types of SD cards and SDIO interfaces as well as Ultra High Speed (UHS) interfaces for SD cards. Managed NAND flash technology reduces the processor’s cycle load of the memory management. The Mentor Graphics eMMC QVIP solution verifies eMMC card and controller interfaces. The ONFI QVIP has a low-pin level interface for the flash memory.

Other features offered by the QVIP library include:

  • A comprehensive test suite;
  • Complete protocol coverage;
  • Assertions checking of complex protocols;
  • Native SystemVerilog OVM and UVM tests and components;
  • SystemVerilog, Verilog, VHDL, and System-C testbench support;
  • Integrated support for verification planning and management; and
  • Transaction-level scoreboarding, analysis, and debug


Flash memory is a extremely fast and a much better choice for most of today’s applications than HDD memory. Flash is relatively expensive, but the benefits outweigh the cost. The family of Flash QVIP from Mentor Graphics makes it easy to quickly create a comprehensive test environment, so you can have confidence that your flash memory devices will work as intended. There are no bugs in the Flash Diner. Enjoy your meal!

About the author

Zeeshan Yousuf is Lead Member Technical Staff in the Questa Verification IP team at Mentor Graphics, specializing in development of XHCI, EHCI, OHCI, SSIC, USB-PD and USB3.0 verification IP. He earned a B.Tech in Computer Science from ACET College, Aligarh in 2010.

Comments are closed.


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors