Want to know a way to verify the registers in a design without having to write code for specific bus interfaces? Or to load up the configuration of a design-under-test without expending simulation time? Those are just two of the features offered by the Register Layer of the Universal Verification Methodology (UVM).
It’s critical to have a good handle on registers: to observe and control them. So we put together a series of videos that build on our YouTube tutorials launched in May 2012 that deal with the basics of UVM for SystemVerilog and e IEEE 1647.
As the videos show, with the Register Layer you can abstract registers access their contents without worrying about the bus protocol used to transfer data in and out of them within the design. When your testbench code writes to one called Reg0, you don’t have to care about its address – that is handled by the UVM register layer. This approach lets you move Reg0 around within the address map and not have to change the verification code.
Among the other features of the Register Layer are frontdoor and backdoor access. With conventional verification techniques, accesses use the same access ports as the design logic. Backdoor accesses do not go through the bus interface but directly into the device, controlled by paths expressed in HDL.
You can use backdoor accesses to shorten simulation: you can configure the design to reflect a certain register state in practically no time through backdoor accesses. You can then start verification from that point. Another useful application of backdoor accesses is to check that write accesses through the frontdoor are happening correctly. To do this you can perform frontdoor writes and then read back through the backdoor. Similarly, you can use frontdoor reads coupled with backdoor writes to ensure that reads performed by the DUT’s logic are not corrupting registers.
You don’t have to be a super-expert on UVM but to make most effective use of the Register Layer features you should have the basics, which you can pick up here. Here are the Register Layer videos:
- Testbench Integration
- Predictor & Auto Predict
- Register Model & Generation
- Register Model Classes
- Register API & Sequences
- Access Policies
- Frontdoor & Backdoor
- Predefined Sequences