If we’d only known then what we know now

By John Ferguson |  No Comments  |  Posted: September 10, 2014
Topics/Categories: EDA - DFM, Verification  |  Tags: , , , ,  | Organizations:

John Ferguson is the director of marketing for Calibre DRC applications at Mentor Graphics. John has worked extensively in the area of physical design verification for the manufacture of leading edge integrated circuits.John Ferguson is the director of marketing for Calibre DRC applications at Mentor Graphics. John has worked extensively in the area of physical design verification for the manufacture of leading edge integrated circuits.

The roadmap for most physical verification technologies is defined by the manufacturing requirements of incoming process nodes. Foundries set very tight deadlines for the introduction of each new process to demonstrate that they are keeping up with Moore’s Law. This means there are firm timelines within which PV providers must implement new capabilities, then have them qualified for production rule files and process design kits (PDKs).

However, this innovation process does not mean that all new physical verification and design for manufacturing technologies apply only to the latest nodes and processes. Some will for inherent reasons, a good example being multi-patterning. But others can and do help designers targeting established nodes.

Advancing analog

The analog designer typically relies on a set of best practices for layout and verification. Consider this example.

For a specific circuit to work properly, two associated transistors must function in exactly the same way. As a result the circuits connecting each transistor must have identical parasitics, which means the neighboring circuits must have the exact same geometric structure, and exactly the same structures nearby within a given radius. To confirm that this is the case, the layout engineer will annotate both transistor layers with a common marker, then add extra rules to check that the transistors with those marker layers match. The layout engineer knows which transistors to address because the circuit engineer told him. The circuit engineer knows because he or she is the artist. Well, you can imagine the scope for error here.

Analog circuitry checks for device centroiding and symmetry constraints, net shielding, voltage-dependent spacing constraints, electromigration analysis and more are usually performed based on these sorts of marker layer - manually placed layers that are prone to human error. Indeed once we step toward automation, traditional tools will still check the marker layers rather than the correctness of the actual circuitry. If the layout engineer puts the marker in the wrong spot, you will likely miss an error.

We are constantly looking for ways to help customers working at established nodes improve and refine their design flows. Advanced physical verification capabilities can help eliminate the dependency on human intervention.

For example, a reliability checking tool like Calibre PERC can identify key design intent requirements such as operating voltages or device/net-specific constraints. These can then be correlated back to the design geometries of interest. Tools like Calibre Pattern Matching can quickly and accurately verify symmetry and centroiding requirements. The advanced fill algorithms found in Calibre SmartFill ensure that symmetry around sensitive devices or nets is retained even under difficult density requirements. When the rules themselves cannot be augmented, automated waiver processing tools like Calibre Automatic Waivers can be used to remove false errors associated with complex structures that may fail standard rule checks but are deemed acceptable by the foundry.

All these examples are based on physical verification technologies originally developed to meet cutting edge design requirements, but which have also been ‘taken back up the flow’ to designs at established nodes.

In the transistor match example, a circuit engineer can add properties or constraints to the schematic to inform the EDA tools which devices need to match. The Calibre PERC deck reads the netlist generated from the schematic, identifies these properties or constraints, and automates checking of pre-qualified rules. Depending on the type of matching required, there may already be sufficient information in the circuit through device connectivity, so that the addition of extra properties or constraints is not needed for some rules. An example of this might be a current mirror, where the transistor ratio ranges are known and the current mirror can be identified simply by the circuit configuration. Because device extraction has been run, as part of Calibre LVS, Calibre PERC knows how the schematic transistors correspond to the layout geometries, so it can tell Calibre DRC to check those transistors with additional and context-specific layout rules.

There are hundreds of these special analog checks that can be carried out thanks to technologies developed for advanced nodes. But the advantages of feeding advanced process-driven innovation back up the chain apply in many other areas.

More than Moore

As cutting edge process nodes entail ever higher NREs, there is an increasing interest in ‘More than Moore’ technologies that seek to extend the life of more established processes. Microelectromechanical systems (MEMS), silicon photonics, and 3D-IC are all today the focus of intense interest and research. They also happen to be technologies where advanced physical verification techniques can simplify life for design companies working at mature nodes.

For example, silicon photonics requires meticulously designed curved structures for devices and interconnects. These structures bring traditional DRC or LVS tools to their knees, causing them to flag millions of false errors. Through the use of advanced physical verification technologies such as equation-based DRC, rules can be written that properly identify real design errors by rendering the necessary curves into a gridded structure like GDSII. Similarly, by leveraging the capabilities of Calibre PERC, the specific curvatures of the devices and interconnects can be verified against the designer’s intent.

The complexity of the curved structures often needed in MEMS can be verified in similar fashion, but simulating MEMS behavior reveals an additional requirement. Traditional parasitic extraction cannot model the behavior of and interaction between these complex structures. They require accuracy only available from a field solver.

However, traditional field solvers lack the performance and capacity needed. This is where an advanced extraction solution such as Calibre xACT 3D comes into play. Combining true field solver technology with the performance and scaling of modern parasitic extraction tools, it provides the verification accuracy required for these MEMS circuits while maintaining targeted tape-out cycles.

Either 2.5D or 3D IC stacking adds another wrinkle. Physical verification solutions have historically relied on layer numbering to indicate vertical separation. For example, if all poly is on GDSII layer 10, then we have, until now, assumed that two butting polygons on layer 10 are physically at the same vertical plane, but a polygon on metal1, identified as GDSII layer 20, is known to be at a different vertical height. Unfortunately, this assumption breaks down for 2.5D or 3D structures when you stack two chips on top of each other.

If the two chips use the same process, you now have two different planes for poly and two different planes for metal1. A traditional DRC tool will not understand that they are different planes. The problem gets worse, though, if the chips use two different processes. Maybe in process 2, the poly is on layer 20? Now you have multiple die, potentially with polygons on the same GDSII layer, at different vertical depths, and perhaps representing completely different geometries. So, designers need a way to tell the DRC tool that the layers on each placed die are separate from all other layers associated with any other die.

A tool like Calibre 3DSTACK that supports physical verification of individual dies, followed by verification of the packaging interfaces, overcomes these issues by differentiating the layers of interest according to each individual die placement. In this way, the die-to-die interactions can be accurately checked, providing designers maximum flexibility to mix die components manufactured with different processes or at different process nodes. This approach can also be extended to generate full assembly layout-extracted netlists for further analysis and simulation.

The latest releases of physical verification and design for manufacturing products offer many such advanced capabilities that extend beyond their initially intended use at incoming process nodes. By being aware of the advanced physical verification capabilities as they become available, designers can use or extend an established process and thereby significantly improve and differentiate their designs.

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