Last year, the IEEE 1666 SystemC Working Group defined the first revision to the popular standard and a separate ballot group approved it as an official IEEE standard. Final edits were recently completed and the standard is now available to users worldwide. In parallel, the Accellera Systems Initiative’s SystemC Language Working Group worked to update its open-source, proof-of-concept reference simulator to incorporate improvements, extensions and enhancements made through the IEEE standardization process so that it complies with the revised standard.
The revised standard defines SystemC with Transaction Level Modeling (TLM) as a single ANSI standard C++ class library for system and hardware design. TLM has become increasingly popular with design and verification engineers and proved useful for not just SystemC users, but also those working with other languages and methodologies, such as Accellera’s Universal Verification Methodology (UVM) with direct support of TLM written in SystemVerilog.
The Accellera Systems Initiative, newly formed from the unification of Accellera and the Open SystemC Initiative (OSCI), has now opened the public review process for the updated reference simulator implementation. To that end, it has made an initial review copy of the SystemC library v2.3 publicly available. It complies with the recently announced IEEE 1666-2011 standard.
The review period provides a great opportunity for individuals and companies to view the implementation of the SystemC library first hand and gain invaluable insights into techniques to design various applications such as semiconductors, models, engineering tools and more. Care and attention has gone into adhering to the standard, but the review process allows the public to offer feedback on this update before it is released for production use.
Accellera wants to know if there are any discrepancies versus the standard. It also wants to understand if users have issues with the installation process and documentation against supported platforms. The public review period ends on March 3, 2012.
Accellera expects the resulting feedback to result in some changes to the final library. This release also allows SystemC users to explore changes made against the SystemC v2.2 proof-of-concept reference. The revision contains the following changes from v2.2:
- Expanded dynamic process capabilities:
- suspend(), resume()
- disable(), enable()
- reset(), kill()
- sc_is_unwinding(), is_reset()
- reset_event(), terminated_event()
- SystemC function and class additions/changes:
- - sc_start(), sc_pause()
- - sc_get_status()
- - sc_time_to_pending_activity(), sc_time_to_pending_activity()
- - sc_vector<>, sc_assemble_vector()
- - set_verbosity_level(), SC_REPORT_INFO_VERB()
- - sc_event_and_list, sc_event_or_list
- - sc_prim_channel::async_request_update()
- Boost library used by SystemC is now in namespace sc_boost rather than boost.
- General bug fixes with details contained in the distribution Release Notes.
- Expanded platform support with details contained in the distribution Releases Notes.
The review ends right after the conclusion of the Design & Verification Conference. The North American SystemC User Group (NASUCG) will join the conference with a half day of SystemC on Monday, February 27.
I expect many reviewers will attend the conference to share their findings first hand.
The NASCUG event is free, but seating is limited, so I encourage you to register now to secure a seat. Following the free event and lunch, there will be a DVCon Tutorial entitled ‘An Introduction to IEEE P1666-2011, the New SystemC Standard.’ (DVCon charges a fee and requires separate registration.
There is one other important note for this public review release for those who depend on TLM. This review version does not contain the slightly updated TLM 2.0.1 distribution. When the official release is complete, it will contain this as IEEE 1666 does include the TLM standard. The release notes will instruct testers on how to deal with the new distribution.
With your help and contributions, we can ensure the SystemC standard and the proof-of-concept reference simulator are ready for deployment in flows, methodologies and EDA products to advance system and hardware design.