Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
Mixed-signal design has gone through a number of inflection points as processes have migrated from processes with features as small as 0.1µm to where we are today at the sub-25nm generations. Design techniques that worked at 90nm were found to work reasonably well at 65nm and even at 45nm. The 28nm process generation introduced new effects, particularly related to drops in core voltages and restrictive design rules that demanded changes in the way analog circuits were laid out.
For example, to avoid metal dishing during chemical mechanical polishing (CMP) processes, the relatively large structures common to analog circuitry needed to be broken up and distributed. Similarly, designers had to pay close attention to poly spacing rules that demanded uniform densities of the material across the chip. Designers had to introduce dummy features that need to be simulated at the layout stage to ensure that changes in spacing from the ideal for that circuit have not pushed the design out of tolerance.
With the arrival of the 20nm and 14/16nm finFET generations, the requirement for double patterning in the diffusion and local-interconnect layers has introduced further restrictions on device placement. A design that is electrically correct in all respects may turn out to be unimplementable because the interconnect does not follow the coloring rules that allow the layout to be split across two complementary masks. The only way to exit the infinite loop and make the circuitry design-rule clean is to alter the layout. Using conventional mixed-signal methodologies this will only be spotted and corrected late in the design cycle.
A number of effects that can render a circuit unusable revolve around transistor stress. Since the 90nm process, strained silicon has become an increasingly important part of process technology. The technique improves mobility and transistor switching performance in an era when the effects due to classic Dennard scaling have slowed. The strain is often imposed by design features such as shallow trench isolation (STI), the composition of the gate oxide as well as, in the case of PMOS devices, layers of silicon germanium diffused under the channel. The degree and nature of the stresses imposed by the surrounding features change based on the position of the transistor within its well as well as surface features such as polysilicon interconnect.
Figure 1 Cadence EAD graphical user interface
As the stresses change so does device performance. At 20nm, the changes in stress have become first-order effects, resulting in large deviations in parameters such as threshold voltage. Since the introduction of the 45nm generation of processes, length of diffusion(LOD) has become an important determiner of transistor performance. To control stress in the source and drain regions, dummy gates need to be used either side of a transistor that does not lie within a regular block. The stress imposed by these dummy elements is sensitive to their length as well as their presence.
Similarly the amount of stress generated by STI is partially determined by its width. Active areas that are closer together to each other will experience different STI-imposed stress than those that are farther apart.
Conventional design under pressure
As the circuit’s performance is controlled more than ever by the relative placement of transistors to each other, it is putting conventional circuit-design approaches under pressure. Traditionally, circuit designers have been able to provide a schematic simulated using average devices to a layout engineer or team and expect the resulting performance to be close enough to only need minor tweaks.
The result of these layout-dependent effects is that the schematic is no longer the design. If not tackled early on, the intensive changes needed to bring the circuit to operate within its specified performance can add excessive time to the design process.
Dummy devices and STI that are tuned to specific dimensions are needed to provide a more even stress profile for the active transistors. If the need for those changes is only seen after the layout has been completed, existing layout often needs to be ripped up and reimplemented in order to provide the additional space. As a result, leading-edge IC companies have been forced to budget as much as 30 per cent of implementation time on fixing layout-dependent problems.
One possible solution is to use layout synthesis to generate a number of possible designs and simulate each in turn to discover the best candidate. However, this wastes a lot of time on circuits that are unsuitable for the task and it is a process that does not reflect the reality of real-world analog. In many cases, there are key devices and sub-circuits that are critical to performance. Other transistors and passive elements are far less sensitive to parametric changes and can tolerate the threshold voltage shifts and other effects that may be caused by being moved towards the edge of a well.
A methodology using partial, iterative layout assisted by electrically aware tools provides a more robust solution to the problem. This flow allows designers to analyze the performance of key transistors and other devices in the context of layout-dependent effects – using models provided by the foundry – without demanding that the rest of the circuit be placed and routed.
Figure 2 Comparison of traditional and EAD flows
Electrically aware tools provide a similar ability as layout-versus-schematic (LVS) to manage and synch connectivity for a partial design and to find out how changes in layout affect the design. If the performance of key devices is not in line with expectations, changes can easily be made to the layout without the need to rip and replace the surrounding circuitry. Furthermore, the performance metrics can be back-annotated and used to improve the accuracy of schematic simulations.
Methodology in action
An example of this methodology in use is a set of transistors required for the matched-pairs current mirror. An initial layout of the devices reveals that stress effects adversely affect transistors at one end of the line of devices used to implement the mirror whereas transistors in the middle of the line provide gain in line with expectations. A solution is to implement dummy devices to ensure that these sensitive transistors gain the advantage of lying well within a group. These dummy devices are easy to add because the rest of the design has not been fixed. In fact, the designer can go further and gauge the impact of adding a second group of dummies to see if the expected improvement outweighs the loss in density, or whether the change in distance between the group and other devices in the circuit degrades performance in other ways.
As the design progresses, other devices can be added from the schematic and their behavior predicted until the complete circuit has been placed and routed. Because performance is checked at each stage, the time-consuming surprises that may be caused by design-rule violations or performance issues is minimized.
Figure 3 Section of routing susceptible to electromigration highlighted in tool
The issues extend to the interconnect. Routing choices made a significant difference to the performance of a circuit. Electromigration (EM), excessive parasitics and IR drop are key issues in advanced nodes. Caused by the gradual movement of atoms in conductors due to momentum being transferred to them by fast-moving carriers, the problem of EM has become more critical in the move to 20nm particularly for power-supply rails because of the need to reduce the thickness of interconnect to meet density requirements in the lower metal layers. In such thin wires, EM hotspots can form that will lose enough metal during operation to cause the circuit and, with it the IC, to fail.
EM checks during layout
Connectivity-driven design provides a solution, allowing designers to check EM and other parameters as the circuit is laid out. Designers can see hotspots and the effects of changes and ‘what-if’ changes, such as adding more than one tap point from the power distribution layers to allow current sharing or by moving tap points so that the power drawn on either side is more balanced. As with placement-sensitive parameters, the results from the analysis can be back-annotated to the schematic for further simulation and additional optimization
Electrically aware tools such as Virtuoso EAD show engineers the current limits, parasitics and other parameters interactively and can display high EM-risk areas for the circuit as it is laid out, providing an early warning of problems before the routing for the rest of the surrounding block is fixed. Tools like EAD enable the layout to be correctly assembled as its contructed and reduce the many iterations between verification and layout that result in significant delays of up to 30% of the overall design cycle.
Recognizing that the physical manifestation of the design is the primary factor in determining the success of an analog block in nanometer processes, iterative design using electrically aware schematic and layout tools provides a more efficient alternative to time-consuming rip-up-and-retry practices. Electrically aware design provides analog and mixed-signal engineers with a way of bringing IC implementation back on schedule.
David White currently directs R&D for Virtuoso Electrically Aware Design products at Cadence Design Systems. He joined Cadence in 2006 through the acquisition of Praesagus, a software company he co-founded in 2001 and where he served as CTO until the merger. Prior to 2001, he co-founded and managed two companies, NeuroDyne and Infolenz and began his career at McDonnell Douglas Aircraft. Dr. White has served as a member of the Advisory Board for the National Science Foundation (NSF) in Washington DC as well as the MIG Advisory Board at MIT.
He has multiple publications in the areas of machine learning and data sciences and was editor and co-author of the Handbook of Intelligent Control, a text written by leaders from the National Science Foundation and the neural network community, published in 1992. Since 1990, he has given invited talks and participated in forums at White House Office of Science and Technology Policy, NSF, DOE, NASA, IEEE, ACM and IJCNN conferences. He has a Doctor of Science Degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.
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