FPGAs are increasingly being used as system accelerators and central processors as a quick way of improving system performance. While this approach garners strong results, FPGA designers are faced with having to juggle multiple pressures to achieve a first implementation quickly, debug and optimize the design for cost/performance, integrate the system software, and ensure the resultant design can accommodate bug fixes and functional updates in the field. Meeting all these requirements takes a careful choice of tools to deliver the best design in the time available with the least risk.
Here are eight tips to think about as you make your choice of tool.
Tip 1 – Reduce your risk
Designers need to perform debug and achieve timing closure as quickly as possible to accelerate validation and software development.
Synopsys’ Synplify Premier offers comprehensive RTL, clock, constraints, IP, port mismatch and error checks upfront, and single-pass debug. The tool can find errors in one synthesis run, at the same time as it completes all the error-free modules, so that bugs can be isolated and multiple fixes can be applied in one step.
The tool has a fast synthesis mode, which applies fewer timing optimizations and has a minor impact on quality of results (QoR). It can also be run on multiple processors at once, for further runtime reductions.
It can also be helpful to partition a design so that the initial RTL can be compiled and run on the FPGA, with bug fixes and incremental functional changes added later. Synplify Premier supports such incremental design strategies.
Tip 2 – Optimize your trade-offs for best QoR
To achieve the best QoR, designers need to write well thought-out constraints for their designs, including finding clocks, creating groupings and relationships, and properly constraining I/O setup/hold, multi-cycle and false paths.
Synplify Premier helps designers by generating information on inferred clocks and creating an FPGA design constraint file. Doing a full compile using the tool’s fast synthesis option, constraints can be created and checked using a constraint-checking utility.
Once the initial design is fully constrained, designers can apply the tool’s physically aware logic synthesis to predict interconnect delays, and correlation tools to ensure better initial constraints. An exploratory place and route feature can adjust the settings for the back-end place and route tools to improve timing and reduce iterations.
Tip 3 - Take new challenges in stride
The very largest FPGAs now use multiple silicon dice interconnected by a silicon interposer. This creates an interconnect delay issue, as signals take much longer to travel between logic elements on different dice than they do on the same die.
Physically aware synthesis gives designers a way to improve timing and timing closure by using a non-disruptive logic synthesis model to do a fast placement estimation that helps improve the optimization decisions made during full synthesis.
Tip 4 – Make sure you can route, as well as place
Predicting routing congestion is difficult. Synplify Premier offers features that can help designers tune their designs for better routability. An exploratory place and route technology can also try multiple design configurations in parallel.
Tip 5 – Parallelism is your friend
Very large FPGA designs can take a long time to synthesize, optimize, place and route. Synplify Premier can run on multiple CPUs to speed up the synthesis and optimization processes. This is particularly useful when optimising the price/performance of the design by trying to implement it in a variety of FPGAs with different logic capacities and speed grades. Since area optimization techniques can change timing constraints, it can be time-consuming to explore the balance of area and performance unless you have a tool that can help designers determine area/speed optimizations.
Tip 6 – Retain your freedom of choice over IP
The systems being built on FPGAs are increasingly made up of in-house design, FPGA vendor and third-party IP blocks. If your tools lock you in to one source of IP, for example from the FPGA vendor, you may have to design blocks for yourself that you could otherwise have licensed on the open market.
Synplify Premier automates IP management, by directly supporting FPGA vendor and third-party IP catalogs, and being able to import IP provided as plain RTL, netlists, or encrypted using schemes such as IEEE P1735.
The tool can also ensure debug visibility and traceability by offering instrumentation capabilities for the design by selecting signals and code branches for sampling/triggering through using the Identify instrumentor. This, coupled with the Identify RTL Debugger, enables results to be observed directly in the RTL source code at system speeds.
Tip 7 – Iterate, iterate, iterate
We’d all like to be right the first time, but in a world where designs are started without a firm specification, being able to iterate quickly is at least as important. Synplify Premier allows designers to use hierarchical design techniques and iterative compilation to iterate quickly. Getting to a first hardware implementation quickly enables early system driver and software development, as well as earlier system validation – and more time to iterate to a better solution.
Tip 8 – Remember the future – and the past
We’ve already seen that using an independent FPGA design tool ensures FPGA designers can utilize the widest choice of IP. It also reduces project risk by giving designers a way to support legacy FPGA devices beyond the support threshold offered by the vendors, and to move existing designs on to new devices if necessary.
Joe Mallett is senior manager, product marketing for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation in the semiconductor and EDA industries. Before joining Synopsys he was a senior product marketing manager at Xilinx Semiconductor, where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL synthesis, IP, and product/segment marketing. He holds a BSEE from Portland State University.
Company infoSynopsys Corporate Headquarters 690 East Middlefield Road Mountain View, CA 94043 (650) 584-5000 (800) 541-7737 www.synopsys.com
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