How eFPGAs will help build the brave new world of AI

By Steve Mensor |  No Comments  |  Posted: April 23, 2018
Topics/Categories: Embedded - Architecture & Design, IP - Assembly & Integration, EDA - IC Implementation, IP - Selection  |  Tags: , , , , ,  | Organizations:

Steve Mensor is vice president of marketing at Achronix with more than 25 years of senior management experience in the FPGA industry. Prior to joining Achronix, he was senior director of marketing at Altera. Mensor holds an MBA from Santa Clara University and a Bachelor of Science degree in Electrical Engineering from UC Santa Barbara.Steve Mensor is vice president of marketing at Achronix with more than 25 years of senior management experience in the FPGA industry. Prior to joining Achronix, he was senior director of marketing at Altera. Mensor holds an MBA from Santa Clara University and a Bachelor of Science degree in Electrical Engineering from UC Santa Barbara.

Even Aldous Huxley had trouble foreseeing a Brave New World where driverless vehicles moved through major metropolitan areas and machines were able to learn. His ‘alphas’ might have had personal helicopters but they were expected to pilot them themselves.

Mr. Huxley, welcome to the era of autonomous driving, medical diagnostics, smart appliances, industrial automation, adaptive websites, financial analytics and so much more – all propelled by machine learning and artificial intelligence.

These applications demand high performance, and in most cases, low latency to respond to changing real-time conditions. For inference functions, the applications will be in end-user products that require low-power consumption. They will not have the plentiful power and cooling that is available for learning functions that reside in cloud-based servers. These applications will also typically have an always-on requirement whether there is a network connection to the cloud or not.

Hardware design must therefore now evolve to meet these and many more opportunities for commercial and industrial systems that are on the horizon. That evolution is likely to involve embedded FPGAs (eFPGAs) in SoCs.

Even Aldous Huxley's visions could not capture all the future holds.

Even Aldous Huxley's visions could not capture all the future holds.

Traditionally, system architects chose ASIC implementations of custom logic and memory managers combined with an embedded CPU, possibly paired with an external FPGA as a coprocessor, to achieve the benefits of a custom processor while retaining reprogrammability. Embedding an FPGA fabric in an ASIC or SoC provides a solution to the drawbacks of a combined SoC and standalone FPGA and the associated issues of passing data between them. One or more eFPGA instances embedded into an SoC enable a designer to tune the performance of the machine learning network on the fly, delivering the high data-transfer bandwidth required to make use of customized engines. Thus, eFPGAs make it possible to achieve the right balance between throughput and reprogrammability, delivering the performance that real-world, machine-learning systems require.

The ability to embed an FPGA fabric on-chip saves significant silicon area versus a combined SoC and standalone FPGA solution. It eliminates the large, power-hungry I/O associated with a standalone FPGA. These die area savings translate into a dramatic reduction in manufacturing costs.

One highly flexible eFPGA IP solution supports the data throughput required in high-performance machine-learning applications. It allows designers to specify a mix of LUTs, LRAMs and DSP blocks to generate a custom FPGA fabric ideally suited to their end application.

Core functions can be augmented by custom blocks with more specialized features that would otherwise be silicon-intensive in programmable logic. Examples of such blocks include TCAMs, ultra-wide multiplexers and memory blocks optimized for pipelined accesses.

Machine-learning algorithms represent a new world for embedded systems. Real-time AI will augment a wide variety of applications, but it can only deliver on its promise if it can be performed in a cost-effective, power-efficient way. Existing solutions such as SoCs paired with standalone FPGAs can be used to support advanced AI algorithms for deep learning, but may not be able to address the increased demands designers are placing on hardware as their machine-learning architectures evolve.

AI needs a careful balance of datapath performance, memory latency and throughput. It requires an approach based on pulling as much of the functionality as possible into the SoC. A single-chip device needs plasticity to be able to handle the changes in structure inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and support for custom algorithms that the market requires.

The new world of real-time, self-learning systems, as we are learning, requires an evolution in hardware design and imaginative system architects. That evolution may be found in eFPGA IP.

More information about the advantages in eFPGA technology can be found in this whitepaper: The Ideal Solution for AI Applications –– Speedcore eFPGAs.

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