Dealing with parasitic-extraction challenges in finFETs and advanced nodes

By Hitendra Divecha |  No Comments  |  Posted: August 7, 2014
Topics/Categories: EDA - IC Implementation, Verification  |  Tags: , , ,  | Organizations:

Hitendra Divecha is senior product marketing manager at Cadence Design SystemsHitendra Divecha is senior product marketing manager at Cadence Design Systems

The emergence of finFETs and 3DICs at advanced nodes provide welcome shots in the arm for electronics design productivity. The benefits, however, don’t come without their challenges, particularly early in the learning curve. I segment these challenges into two main categories:

  • Increasing complexity
  • Modeling challenges.

The issues are not just about tighter geometries and new design rules, which come with every new process node. The number of process corners is exploding, and — specifically for finFET devices — there is an explosion in the parasitics, specifically coupling capacitances and resistances. This increases the design complexity and workload — the netlist is getting bigger and bigger and as a result there is an increase in extraction runtimes for SoC designs post-layout simulation and characterization runtimes for custom/analog designs.

Vertically challenged

Now let’s look at modeling challenges and specifically examine finFET devices. Here, we see the introduction of local interconnects. There are also secondary and third-order manufacturing effects also that need to modeled accurately. Performance and turn-around times key issues but if you can’t provide accuracy for these devices — especially as it relates to the foundry golden data — the customer has to deal with the additional burden of needing to over-margin their designs, which leaves performance on the table.

You don’t make friends that way.

As we push into these advanced nodes, we’re finding that extraction, as a subset of verification effort, is taking up more time. Extraction and time-to-signoff times are increasing, and designers’ their time-to-market is shrinking. It can take anywhere from six to eight weeks for designers to close the signoff loop. Extraction is obviously a critical step in this loop. We have been told by our customers, though, the extraction runtime varies based on the design sizes and types, but full flat extraction at these advanced nodes can take up to three days with their current extraction tools. This puts enormous amount of pressure on our customers’ ability to have design closure in a timely manner to meet their time-to-market pressures.

Now let’s look deeper at the challenges in these nodes and their effect on signoff extraction. The number of interconnect corners has exploded partly also due to the introduction of double-patterning technology (DPT) that was first introduced at 20nm and which has been carried over to 16/14nm finFETs. Second, design sizes are increasing. At 20nm and below, there are more than 70 million net designs. With more corners and larger design sizes, extraction goes from taking a day to a few days to complete.

Parasitics explosion

Now, consider that there are 155x more resistances to consider for finFET than 28nm devices. This growth means bigger netlists, which impacts post-layout simulation performance and requires faster simulation runtime. Tools need to model three different resistance types: contact resistance, spreading resistance, and extension resistance. And consider this: the thickness of the 3D gate introduces new capacitances. From finFET to fringe capacitances, double patterning, and more, the modeling features have just grown more complex, and that stretches out extraction runtime.

I want to emphasize that these are new problems that we’re attacking. Existing flows and tools in some cases are perfectly acceptable for certain designs and older nodes. But as I’ve pointed out, advanced nodes are a different ballgame. In most cases, different extraction engines are used in implementation and signoff, resulting in poorly correlated results that have a negative impact on design closure. Consistent extraction engines throughout the flow — meaning implementation and signoff — is a linchpin to our customers’ time-to-signoff time as this reduces the number of ECO loops they have to go through.

Given the heightened challenges for parasitic extraction with finFETs and advanced nodes, we’ve brought a massively parallel architecture to bear on the problem. Quantus QRC, which Cadence recently announced, offers up to five times better turnaround time for both single and multi-corner extraction versus traditional extraction tools in the market today. It provides scalability to hundred of CPUs and machines and delivers best-in-class accuracy for finFET designs measured against the foundry’s golden standard. In some cases users can cut extraction runtimes to ten hours from three days.

New challenges call for new solutions, pure and simple, if we are to wrestle the explosion of parasitics to the ground, exploit the benefits of vertical structures, and advanced nodes and keep engineering productivity humming along.

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