Bring decaps under control with automated analysis

By Sam Chitwood |  No Comments  |  Posted: March 19, 2014
Topics/Categories: PCB - Design Integrity, Layout & Routing  |  Tags: , ,  | Organizations:

Decoupling capacitor counts are increasing as PCBs deploy more advanced silicon. But you can use automated analysis to bring counts and costs under control.

When dealing with high-performance processors and FPGAs, the designer is faced with thousands of solutions to the problem of providing sufficient decoupling capacitors (decaps). Simply substituting individual capacitors can shift the signal-integrity performance of the PCB and its associated manufacturing cost. By making smarter choices on decoupling capacitors and their layout, it becomes possible to not only boost performance and cost-effectiveness but reduce the board space needed for decoupling.

Given the number of decap options it is almost impossible for a single designer to make the choice as to which is the best, even for what is nominally the same layout. Even with the availability of detailed simulation tools to verify power distribution network (PDN) performance, it is often not clear how to make decap implementation tradeoffs.

Pre-layout decisions tend to add more decaps than truly needed. Manufacturers will often recommend one decap per power pin to help ensure that the complex power needs of their processor or FPGA products are met comfortably – and that the part works. But this recommendation if followed to the letter is highly likely to result in over-design, and by a large margin.

Traditional techniques

Selection and placement of decaps is often based on experience and rules of thumb. Although it is easier to remove extra decaps than to add more during post-layout verification, over-design not only adds the cost of unneeded decaps, but may unnecessarily force use of extra PCB layers due to blocked routing channels that need not be blocked. Furthermore, design based on rule-on-thumb can lead to layouts that meet minimum requirements but perform more poorly than optimized layouts based on fewer decaps.

In one example, a design containing close to 130 decaps exhibited peaks in impedance at certain frequencies in the gigahertz range that were likely to result in significant noise. The situation could be avoided by a number of different layouts that used as few as a third of the original total decaps.

Explore the decap space

The problem that faces the engineer is that even using simulation there is not enough time to explore the decap-design space. Traditionally, it has been an iterative process where the designer may use experience to get in the right ballpark with a few designs and then simulate and tweak them iteratively. But time pressures being what they are, the designer may only be able to try out a half dozen options before having to commit to one of the tested layouts. While this local minimum may be good enough, a search over a much larger design space can reveal a global minimum that reduces cost and complexity but which offers high performance.

What is needed is a tool that can perform much of this search automatically and provide the designer with more informed choices as to the cost and complexity of the decap network. Successful selection of the type and quantity of decaps and their placement locations depend on many factors. Included in the factors are: device switching current, target impedance profiles, capacitance and inductance (ESL) of the decaps, mounting inductance of each decap and device, and PDN inductance between device and decap.

Analytical approach

Cadence Sigrity OptimizePI was designed to provide an analytical basis upon which to make decisions regarding PDN design tradeoffs and is the first to consider in-product costs. The tool, which operates in the frequency domain, supports two usage models. One is focused on pre-layout guidance on decap types and how many should be placed on the top/bottom of the design and under the devices. This helps to dramatically reduce over-design at an early stage in the design flow, where it can yield the greatest benefit to the overall design.

The workflow for OptimizePI

Figure 1 The workflow for OptimizePI

Post-layout analysis focuses on optimizing a board design that is almost complete, and provides options to minimize disruption to the layout if repositioning of components would result in too much turnaround time. The tool considers thousands of design alternatives in a completely automated manner and provides a short list of optimal decap schemes from which to select the most appropriate tradeoff for the design.

In post-layout mode, OptimizePI takes as its input the PCB layout. From there, the user matches the decaps used in the design with those stored in the tool’s library. As standard, the tool has thousands of decap definitions with various ESL and ESR ratings and different resonant frequencies, as well as their associated bill of materials (BOM) cost. The tool will use this library to analyze the effect of different distributions.

For each decap, the user can select how they will substituted – if at all. For example, capacitors included to reduce EMI can be fixed in place so that the optimization focuses only on those used for power smoothing. Capacitors that can be substituted may be set to be replaced only by a device of the same size – to allow the same layout to be used – be swapped for a smaller device or removed completely. By setting the substitution to be for the same device, the device can only be removed by the tool’s proposal or left as it is.

Effectiveness curve

Following the analysis, the designer is presented with a curve showing the effectiveness of each set of decaps based on the engineer’s criteria, such as cost, area and number or a combination of all three. Plots on the frequency vs impedance graph shows how each performs electrically so that the engineer can intelligently trade performance against cost.

The tool can also indicate how small layout changes can improve overall performance. For example, high impedance at high frequencies for a large number of candidate decap selections may be symptoms of sub-optimal choices over stack-up or routing, leading to higher than desired mounting inductance. Reports that show higher-than-expected inductance values for individual decaps can show the engineer areas where improvements in layout can benefit overall performance.

Graphs show performance against capacitor count and impedance charts for the different options

Figure 2 Graphs show performance against capacitor count and impedance charts for the different options

Even for designs that have undergone pre-layout analysis, using OptimizePI it is typical to reduce decap cost by 15 per cent while maintaining or improving performance during post-layout optimization. For decap implementations that are over-designed from the beginning, the decap cost savings are often 50 per cent or more with the potential for significant PDN performance improvements.

As a result, automated optimization of decaps can provide sizeable savings even for PCB designs that are close to the point of release to manufacture.

About the author

Sam Chitwood is a product engineer at Cadence Design Systems.

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