x86

April 9, 2013
tdf-calyptoamd-mar13-featim

How AMD implemented efficient clock gating analysis for Jaguar

The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.

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