virtual prototype

February 12, 2013

How virtual prototyping enabled Altera’s SoC FPGAs

The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.
Article  |  Topics: Embedded - Architecture & Design, - Embedded Topics  |  Tags: , ,   |  Organizations: ,
November 16, 2012
Synopsys Virtualizer screen shot

The Shift Left: how virtual prototyping reduces risk

The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.
October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
September 18, 2012
Bill Neifert

Virtual prototyping moves further into the mainstream

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.
Expert Insight  |  Topics: EDA - ESL, Verification  |  Tags:
April 25, 2012
Mentor's Veloce emulator

Emulation delivers energy efficiencies and economies of scale

Can emulation save energy and space, as well as time, during the verification process? Some argue so.
April 5, 2012

Overcoming increasing PCB complexity with automation

Advanced PCB and IC technologies have to be matched with advanced design and analysis tools if companies are going to produce board designs that are right first time, on time.
January 23, 2012

Seven habits of highly effective virtual prototypes

Virtual prototyping is not a new technique, but the advent of transaction-level modeling and an increased focus on seven key requirements for their effective use means that today's versions are much more broadly applicable and comparatively future proof.
Article  |  Topics: EDA - ESL  |  Tags: ,
June 1, 2010

A matter of timing

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
June 1, 2009

Using TLM virtual system prototype for hardware and software validation

The article describes how a methodology based around scalable transaction level modeling (TLM) techniques can be used to enable software design to begin far earlier in a design fl ow and thus allow companies to bring designs to market faster, particularly in time-sensitive sectors. It is based on the creation of high-level hardware models that […]

December 1, 2008

Streamlining software development for a hardware ecosystem

Software accounts for more than half the development cost for a complex system-on-chip (SoC) platform at the 45nm process node or below. The availability of fundamental software such as compilers, debuggers, operating systems and industry-specific middleware determines the success or failure of a chip design. In simple terms, if there is little or no software […]

Article  |  Topics: EDA - ESL  |  Tags: , ,

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