verification IP

September 6, 2022
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Let there be no misunderstanding: Verifying CXL cache coherency

How to work with the Compute Express Link and protocols such as MESI to maintain cache coherency.
Article  |  Topics: Uncategorized  |  Tags: , ,   |  Organizations:
January 19, 2017
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USB Type-C: Verification challenges and solutions

The USB Type-C connector is versatile and already gaining traction in laptops, tablets and desktops. Here's how verification IP plays an important role in achieving the best implementation.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations:
December 20, 2016
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Nine effective features of NVMe VIP for SSD storage

The open NVMe standard is helping non-volatile memory storage reach its true potential with increasingly rich verification support
Article  |  Topics: EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
March 3, 2016

What’s cooking at the Flash Diner?

Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
January 22, 2016
Verification IP, Mentor Graphics, Jan 16, Featured Image

Easing the use of APIs for verification IP stimuli

How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
Article  |  Topics: IP - Selection, EDA - Verification  |  Tags: ,   |  Organizations:
November 2, 2015

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
October 19, 2015
Nasib Naser is senior staff corporate applications engineer in the verification group for Synopsys.

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Expert Insight  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , ,   |  Organizations:
September 18, 2015
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How PHY verification kits overcome traditional VIP limitations

Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
May 23, 2013
Cost of verification

Facing the verification management challenge

The growing verification challenge, and how to address it by coordinating multiple debug strategies.

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