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September 23, 2015
amd-semitai-featim

Mounting Fiji: How AMD realized the first volume interposer

AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?
Article  |  Topics: EDA - DFM, DFT, IC Implementation  |  Tags: , , , , , , ,   |  Organizations: , , , ,
June 22, 2014
Preview image for monolithic 3D integration

Monolithic 3DIC for SoC

Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
June 18, 2014
Parasitic Extraction Featured Image

Full 3D-IC parasitic extraction

How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
Article  |  Topics: EDA - DFM  |  Tags: , ,   |  Organizations:
September 24, 2013
Hybrid memory cube architecture

DRAM interfaces for mobile and networking designs

Mobile and networking platforms need high bandwidth, low power consumption, and small footprint. These needs drove standards, such as LPDDR4, Wide I/O 2 and Hybrid Memory Cube.
Article  |  Topics: IP - Selection  |  Tags: , , , , , , ,   |  Organizations:
August 12, 2013
Steve Smith of Synopsys

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
May 8, 2013
3D-IC cross-section

Eight requirements for 3D-IC design

Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
April 17, 2013
Xilinx 3D-IC interposer featured image

3D-IC integration – a stepwise approach

2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.
Article  |  Topics: EDA - IC Implementation  |  Tags: , ,   |  Organizations:
April 10, 2013
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , ,   |  Organizations:
December 12, 2012
Xilinx 3D-IC interposer featured image

Enabling 3D-IC design

Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
August 21, 2012

2.5D-IC, 3D-IC, and 5.5D-IC – stacked-die integration

A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.

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