TLM

December 1, 2008

Tightening the loop on coverage closure

The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so […]

Article  |  Topics: EDA - Verification  |  Tags: , , ,
March 1, 2007

System-level design matures

How do we bridge the gap between the highly abstract view provided by traditional system-level design and the detailed implementation in RTL? The article answers this question by describing the components within an ESL methodology and illustrating its use via customer case studies. The methodology uses the ARM RealView SoC Designer tool and Tenison Design […]

Article  |  Topics: EDA - ESL  |  Tags: ,   |  Organizations:

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