TLM

June 7, 2017
Diag 4

Staging virtual prototype bring-up for faster software development

How staging virtual prototype bring-up can accelerate the development of embedded software in complex systems.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , , ,   |  Organizations:
December 16, 2013
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Consistency key to gaining the advantages of IP integration

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
November 1, 2013
Jack Erickson is director of product management at Cadence Design Systems.

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Expert Insight  |  Topics: EDA - ESL  |  Tags: , , ,   |  Organizations:
February 9, 2012
Dennis Brophy

New SystemC reference simulator open for public comment

A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy. Here's what’s new in the proof-of-concept simulator, and how you can participate to refine the Accellera Systems Initiative’s work for standardization.
Expert Insight  |  Topics: EDA - ESL  |  Tags: ,   |  Organizations:
September 10, 2010

Parallel simulation of SystemC TLM 2.0 compliant MPSoCs

Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
Article  |  Topics: IP - Assembly & Integration, EDA - ESL  |  Tags: , ,
June 1, 2010

A matter of timing

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
September 2, 2009

Part 3 – A unified, scalable SystemVerilog approach to chip and subsystem verification

The article describes LSI’s work on the use of a single SystemVerilog-based (SV) verification environment for both the chip and its submodules. The environment is based on SV’s Advanced Verification Methodology (AVM) libraries, although alternatives are available. One particular reason for choosing AVM was that LSI wanted to leverage its transaction-level modeling capabilities as well […]

Article  |  Topics: EDA - Verification  |  Tags: , , ,
June 1, 2009

Bridging from ESL models to implementation via high-level hardware synthesis

The article describes a methodology that bridges the gap between SystemC transaction-level models (TLMs) that are used for architectural exploration and SystemC cycle-accurate models of hardware that typically follow much later in a design flow, after many sensitive decisions have been made. The behavior of the cycle-accurate models can be verified in the complete system […]

Article  |  Topics: EDA - ESL  |  Tags: , ,
June 1, 2009

Using TLM virtual system prototype for hardware and software validation

The article describes how a methodology based around scalable transaction level modeling (TLM) techniques can be used to enable software design to begin far earlier in a design fl ow and thus allow companies to bring designs to market faster, particularly in time-sensitive sectors. It is based on the creation of high-level hardware models that […]

December 1, 2008

Tightening the loop on coverage closure

The article describes how methodologies such as graph-based intelligent testbench automation will help engineers efficiently create verification scenarios and stimuli. This is a powerful way of enhancing advanced verification environments and reducing common verification headaches (e.g., reaching coverage goals). Such strategies can help to free up resources, in terms of time, people and hardware, so […]

Article  |  Topics: EDA - Verification  |  Tags: , , ,

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