test

August 27, 2020
total critical area feature - headline image

How to optimize test patterns based on critical area

The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations: ,
October 10, 2014
Dr Yervant Zorian, Synopsys

Finding and fixing faults in finFET memories

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - DFM, DFT  |  Tags: , , , ,   |  Organizations:
July 23, 2014

20nm

The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.

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