SoC

August 14, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
March 19, 2018
Dr Lauro Rizzatti, verification consultant

How hardware emulation helps drones take flight

In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
October 14, 2016
networking-soc-mentor-ixia-featim

Taking risk out of software-driven networking SoCs

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
Article  |  Topics: EDA - DFT, - Uncategorized, EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
April 27, 2015

Enabling FPGA prototyping of large ASIC and SoC designs

How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
July 3, 2014
Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
January 7, 2014
Neil Songcuan is a senior product marketing manager, responsible for the FPGA-based Prototyping Solution at Synopsys.

Using HAPS to streamline IP to SoC integration

The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - IC Implementation  |  Tags: , ,   |  Organizations:
October 7, 2013
Adnan Hamid is co-founder and CEO of Breker Verification Systems. Prior to starting Breker in 2003, he worked at AMD as department manager of the System Logic Division. Hamid graduated from Princeton University with Bachelor of Science degrees in Electrical Engineering and Computer Science and holds an MBA from the McCombs School of Business at The University of Texas.

Think like designers to fill the SoC verification gap

Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations:
April 30, 2013

Knock down the wall to SoC integration

SoC integration can be accelerated by using virtualization to make the benefits of emulation more accessible to both hardware and software engineers.
Article  |  Topics: Embedded Topics, Embedded - Integration & Debug  |  Tags: , , ,   |  Organizations:
April 24, 2013
Mick Posner, Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Expert Insight  |  Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,
April 1, 2013

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Article  |  Topics: IP - Assembly & Integration, EDA - DFM, Verification  |  Tags: , , ,   |  Organizations: ,

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