Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
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