sequential equivalence checking

June 18, 2018

Formal fault analysis for ISO 26262: Find faults before they find you

How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
November 6, 2017

Using sequential equivalence to verify clock-gating strategies

Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
August 31, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The evolution of formal verification – Part Two

Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
July 21, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The evolution of formal verification – Part One

Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
May 30, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.

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