sequential equivalence checking

November 6, 2017
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Using sequential equivalence to verify clock-gating strategies

Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
August 31, 2017
Ashish Darbari is director of product management at OneSpin Solutions.

Doc Formal: The evolution of formal verification – Part Two

Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
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Ashish Darbari is director of product management at OneSpin Solutions.

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Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.

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