RTL

February 18, 2016
RTL Floorplanning - Featured Image

How new RTL floorplanning techniques speed physical design

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
September 30, 2014
Pranav Ashar

The evolution of lint

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
May 29, 2014

Lint

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Guide  |  Topics: EDA - Verification  |  Tags: , , , , , ,
April 9, 2013

How AMD implemented efficient clock gating analysis for Jaguar

The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
April 25, 2012
Richard Pugh

No more spaghetti

Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
April 5, 2012

Assertion-based verification

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.

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