RTL signoff

May 29, 2014

Lint

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Guide  |  Topics: EDA - Verification  |  Tags: , , , , , ,
October 16, 2013
Piyush Sancheti, vice president of product marketing at Atrenta.

The requirements for complete RTL signoff

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:

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