reset

March 1, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Exploiting the power of reset in formal verification

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
April 16, 2014
Pranav Ashar

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 27, 2014
Atrenta CDC

Spot the difference between false and real clock violations

Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
October 31, 2013

X propagation

X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.
March 11, 2013
Metastability at clock boundary

Clock-domain and reset verification in the low-power design era

The multiple clock domains on today's SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
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