regression

May 13, 2016
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How continuous integration with Jenkins serves verification flows

A technique built for software development is now helping hardware engineers master increasingly complex verification flows.
Article  |  Topics: Uncategorized, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
July 25, 2014
Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Expert Insight  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , , ,   |  Organizations: , ,
January 13, 2014
Formal verification aids RTL verification

Formal verification enables Agile RTL development

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:

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