PSL

May 28, 2014

Formal verification

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
April 5, 2012

Assertion-based verification

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
March 1, 2006

Integrated, comprehensive assertion-based coverage

Introduction The emergence of the SystemVerilog and PSL assertion languages promises to improve the effectiveness of existing verification flows. First, assertions give better local observability of the functionality they represent. Second, the assertions augment the textual specification to provide a more formal, executable representation of the functionality. Third, since the assertion languages have common semantics […]

Article  |  Topics: EDA - Verification  |  Tags: , ,

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