process shrink

December 3, 2013
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:
September 24, 2013

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
Article  |  Topics: EDA - DFM  |  Tags: , , ,
June 1, 2010

First fabless, now labless

Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain
Article  |  Topics: EDA - DFM  |  Tags: , ,
May 1, 2010

Manufacturability and yield toward 22nm

This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]
Article  |  Topics: EDA - DFM  |  Tags: , , ,
May 1, 2010

Manufacturing a profit

DFM is essential to differentiating your products in the market, says Luigi Capodieci
May 1, 2010

DFM matures

Engineering managers need to get their priorities in order for incoming process nodes, says analyst Gary Smith
Article  |  Topics: EDA - DFM  |  Tags: , ,
May 1, 2010

Not the one that got away

The purpose of this special issue of EDA Tech Forum is to try and cut through some of the confusion and even frustration that surrounds DFM as a concept. We cannot promise “DFM for Dummies,” but we do hope to give you a sense of how you might manage the process.
Article  |  Topics: EDA - DFM  |  Tags: , ,
April 14, 2010

Solving the next parasitic extraction challenge

A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]
September 1, 2009

System level DFM at 22nm

The article provides an overview of one common theme in the papers presented at a special session of the 2009 Design Automation Conference, Dawn of the 22nm Design Era. As such, we would recommend that readers wishing to access still more detail on this topic (in particular, on device structures for 22nm and project management […]

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