Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
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