power grid

October 6, 2014
Power grid signal track blocking

ARM, TSMC design explores 16nm finFET issues

ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,
October 11, 2013
Mentor Power Grid article featured image

Power grid analysis for 2.5D and 3D IC systems

PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , ,   |  Organizations:
June 2, 2011

Efficient RC power grid verification using node elimination

To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
Article  |  Topics: EDA - Verification  |  Tags: , ,

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